1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an internal voltage generating circuit of a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor memory devices, such as Dynamic Random Access Memory (DRAM) devices, are trending toward high speed, low power consumption, high-density process and low operation voltage. Most semiconductor memory devices include an internal voltage generator that uses external power supply voltages (e.g., VDD and VSS) to generate internal voltages necessary to operate various internal circuits. The main issue in designing the internal voltage generator is to maintain a constant internal voltage of a desired level.
Examples of the internal voltages include a core voltage VCORE supplied to a core region including a memory cell array, a high voltage VPP used to drive a word line or used in an overdriving operation, a back-bias voltage VBB supplied as a bulk voltage of an NMOS transistor of a core region, a cell plate voltage VCP used as a plate voltage of a memory cell capacitor, and a bit line precharge voltage VBLP used to precharge a bit line. Hereinafter, a core voltage generator for generating a core voltage VCORE will be described as an example.
FIG. 1 is a block diagram of a conventional core voltage generator included in a semiconductor memory device. FIG. 2 is a circuit diagram of the conventional core voltage generator illustrated in FIG. 1.
Referring to FIGS. 1 and 2, the core voltage generator includes a driving unit 110 configured to drive a core voltage VCORE, and an operation period defining unit 120 configured to detect a voltage level of the core voltage VCORE with respect to a reference voltage VREFC and define an operation period of the driving unit 110.
The driving unit 110 is a pull-up driving unit configured to pull-up drive the core voltage VCORE. The driving unit 110 receives an output signal VGS_PASS of the operation period defining unit 120 as a gate input, and includes a PMOS transistor having a source and a drain connected between a power supply voltage (VDD) terminal and a core voltage (VCORE) terminal.
The operation period defining unit 120 includes a dividing unit 122 configured to divide an internal voltage in a predetermined division ratio, a comparing unit 124 configured to compare the reference voltage VREFC and a feedback voltage VFBK fed back by the dividing unit 122 and output the comparison signal VGS_PASS, a sinking unit 126 connected to the core voltage (VCORE) terminal to decrease the voltage level of the core voltage VCORE when the voltage level of the core voltage VCORE increases excessively, and a precharge unit 128 configured to precharge an output (VGS_PASS) terminal of the comparing unit 124. The dividing unit 122 includes one or more resistors between the core voltage (VCORE) terminal and a ground voltage (VSS) terminal with respect to an output terminal of the feedback voltage VFBK. Since the dividing unit 122 has resistors with the same voltage difference between both ends, the feedback voltage VFBK corresponds to a half core voltage VFBK that is a mean voltage between the core voltage VCORE and the ground voltage VSS. The comparing unit 124 includes a current-mirror differential amplifier, and may include an NMOS type.
A method for driving the conventional core voltage generator is will be described below with reference to FIG. 3.
FIG. 3 is a timing diagram illustrating a method for driving the conventional core voltage generator illustrated in FIG. 1.
Referring to FIG. 3, the dividing unit 122 generates the feedback voltage VFBK corresponding to the core voltage VCORE, and the comparing unit 124 continuously compares the feedback voltage VFBK with the reference voltage VREFC.
When an internal circuit (not illustrated) using the core voltage VCORE operates and a load current IL is generated, the voltage level of the core voltage VCORE decreases. Accordingly, the voltage level of the feedback voltage VFBK outputted from the dividing unit 122 decreases, and the driving unit 110 operates according to the comparison signal VGS_PASS outputted from the comparing unit 124. As the driving unit 110 operates, the voltage level of the core voltage VCORE increases to a target level. Thereafter, an operation of the driving unit 110 is interrupted by the dividing unit 122 and the comparing unit 124.
When the voltage level of the core voltage VCORE increases excessively due to the operation of the driving unit 110, the voltage level of the core voltage VCORE is adjusted to the target level by the sinking unit 126. Also, the precharge unit 128 precharges the output (VGS_PASS) terminal of the comparing unit 124 in a precharge period to restrict the operation of the driving unit 110.
However, the conventional core voltage generator has the following limitations.
As illustrated in FIG. 2, when the load current IL is generated excessively by the internal circuit, an excessive voltage drop of the core voltage VCORE occurs in the initial supply period of the core voltage VCORE. In this case, it takes a considerable time for the core voltage VCORE to reach the target level. That is, as a variation ΔV of the core voltage VCORE increases, it takes a longer recovery time for the core voltage VCORE to reach the target level. Thus, in the event of an excessive voltage drop of the core voltage VCORE, an unstable state of the voltage level of the core voltage VCORE continues due to a long recovery time of the core voltage VCORE, and the internal circuit malfunctions due to the unstable core voltage VCORE.